The present invention relates to complementary metal oxide semiconductor (CMOS) device manufacturing, and in particular to a method of fabricating an ultra-shallow junction in a CMOS device in which the transient enhanced diffusion (TED) of boron and other like dopants is substantially eliminated.
Advances in the miniaturization of CMOS devices have been a key driving force behind the explosive growth of various network centric computing products such as ASIC high-speed microprocessors and memories, low power hand-held computing devices and advanced multi-media audio and video devices. Smaller CMOS devices typically equate to faster switching times which in turn lead to faster and better performing end user systems.
The process of miniaturizing CMOS devices involves scaling down various horizontal and vertical dimensions in the CMOS device. In particular, the thickness of the ion implanted source/drain junction of a p or n-type transistor is scaled down with a corresponding scaled increase in substrate channel doping. In this manner, a constant electric field is maintained in the transistor channel which results in higher speed performance for scaled down CMOS transistors. For example, for a 0.1 xcexcm CMOS device, the source/drain extension junction closest to the transistor channel is as shallow as 30 nm and has a channel doping as high as 1xc3x971018 atoms/cm3.
The formation of source/drain extension junctions in CMOS devices is typically carried out in the prior art by ion implantation in appropriately masked source/drain regions of a Si substrate with boron (p-type) or arsenic and phosphorus (n-type) dopants. Although ion implantation is used in creating the source/drain regions, ion implantation causes crystal damage to the Si substrate as well as the formation of excess Si interstitials.
As is known to those skilled in the art, Si interstitials are displaced Si atoms created by ion bombardment of the crystalline Si substrate. During subsequent thermal annealing, the presence of excess Si interstitials greatly enhances (10 to 1000 times) the normal diffusion of dopants through the Si substrate and results in a much deeper source/drain junction and a poorer junction profile.
This greatly enhanced diffusion of dopants due to the presence of excess Si interstitials around the dopant atoms is commonly referred to in the prior art as transient enhanced diffusion (TED). In particular, the relatively high diffusivity of small boron dopants in combination with ion channeling and transient diffusion makes the fabrication of small p-type CMOS devices difficult. The aforementioned combination also represents a major hurdle that needs to be overcome further miniaturization of the CMOS device technology can occur.
Several prior art approaches have attempted to reduce the transient enhanced diffusion for shallow junction formation. In one approach, a carbon co-implant was used to reduce the transient diffusion of boron dopant during rapid thermal annealing (RTA). The conditions employed in forming the shallow junction using carbon co-implantation were as follows: 2 keV boron shallow implant, dose 1xc3x971015/cm2, carbon implant (energy not reported), carbon dose 2xc3x971014/cm2. Rapid thermal anneal (RTA) conditions were 950xc2x0 C., 30 seconds, or 1050xc2x0 C., 30 seconds, respectively.
Although carbon co-implant is effective in reducing the transient diffusion of boron, this method suffers from the disadvantage that a high density of residual defects remain after RTA. This is the case even using high temperature anneal conditions (1050xc2x0 C., 30 seconds). The high density of residual defects results in high electrical leakages for the shallow junction.
Another approach reported by T. H. Huang, et al. (xe2x80x9cInfluence of Fluorine Preamorphization on the Diffusion and Activation of Low-energy Implanted Boron during Rapid Thermal Anneal,xe2x80x9d Appl. Phys. Lett., (1994) Vol. 65, No. 14, p. 1829) used fluorine co-implants to reduce the transient diffusion of boron dopants during rapid thermal anneals. The conditions used in this reference for shallow junction formation are as follows: fluorine implant, 40 keV ion energy, dose =2xc3x9710xe2x88x925/cm2, 5 keV boron or 23 keV BF2 shallow implants. In the process disclosed by Huang, et al., the wafers were rapid thermal annealed at 1000xc2x0 C., 1050xc2x0 C. and 1100xc2x0 C. for 30 seconds. Although the presence of fluorine implants reduced the transient boron enhanced diffusion during RTA, this prior art method also suffers from the disadvantage that residual defects remain after 1000xc2x0 C., 30 seconds anneal. Residual defects can only be removed with 1100xc2x0 C., 30 seconds anneal. However, substantial dopant motion occurs at this higher temperature and therefor ultra-shallow junctions cannot be formed.
Another approach reported by S. Saito entitled xe2x80x9cDefect Reduction by MeV Ion Implantation for Shallow Junction Formation,xe2x80x9d Appl. Phys. Lett., (1993) Vol. 63, No. 2, p. 197 used fluorine implants for preamphorization (40 keV, 1xc3x971015/cm2), shallow implant; boron at 10 keV and 5xc3x971015/cm2. This was followed by ion implantation of either fluorine or silicon at 1 MeV energy or arsenic at 2 MeV energy. The dose used for the MeV implant was between 5xc3x971014 to 5xc3x971015/cm2. The samples were rapid thermal annealed at 1000xc2x0 C. or 1100xc2x0 C. for 110 seconds.
Under these experimental conditions, Saito demonstrated that the MeV implants were effective in reducing the boron transient diffusion with and without fluorine preamphorization. This reference also demonstrated that maximum reduction in boron dopant diffusion was achieved when both fluorine preamorphization and MeV fluorine implants were used. However, as mentioned in the prior art earlier, use of fluorine implants creates residual defects and requires temperatures as high as 1100xc2x0 C. for low leakage junctions to be formed.
In each of the prior art references mentioned hereinabove, high energies were used to implant boron (2 to 10 keV) or BF2 (23 keV) into semiconductor materials. These energy ranges are however unsuitable to create an ultra-shallow boron dopant junction below 50 nm. All the junction depths created by the prior art techniques are between 60-100 nm. Although the combination of high temperature ( greater than 1000xc2x0 C.) and long annealing times (10 to 30 seconds) minimizes residue defects due to carbon or fluorine co-implants, it inhibits the formation of ultra-shallow junctions.
Despite the current advances made in the field of microelectronics, there is still a need for providing a new and improved method which provides an ultra-shallow junction in CMOS devices while overcoming all of the drawbacks mentioned hereinabove.
One object of the present invention is to provide a method of fabricating ultra-shallow junctions in microelectronic devices. The term xe2x80x9cultra-shallowxe2x80x9d as used herein denotes a junction whose depth is less than 50 nm from a top surface of a semiconductor substrate. More preferably, the present invention forms junctions having a depth of from about 10 to about 40 nm.
Another object of the present invention is to provide a method of forming ultra-shallow junctions wherein the transient enhanced diffusion (TED) of boron and other like dopants is substantially eliminated.
A further object of the present invention is to provide a method of fabricating ultra-shallow junctions wherein the depth of the junction is not effected by a subsequent high temperature annealing (i.e., activation annealing or silicide) step.
These as well as other objects and advantages can be achieved in the present invention by introducing a material into the CMOS structure that produces excess vacancies in the substrate which can combine with and substantially annihilate the interstitials during a subsequent heating step before they can cause excess dopant diffusion.
Specifically, the method of the present invention, which achieves all of the above mentioned objects and advantages, comprises the steps of:
(a) implanting a dopant into a surface of a Si-containing substrate so as to form a doped region therein;
(b) forming a metal layer on said Si-containing substrate; and
(c) heating said metal layer so as to convert said metal layer into a metal silicide layer while simultaneously activating said doped region, whereby vacancies created by said heating combine with interstitials created in step (a) so as to substantially eliminate any transient diffusion of said dopant in said Si-containing substrate.
In one embodiment of the present invention, the metal layer is formed in close proximity to the doped region provided in step (a). In another more highly preferred embodiment, the metal layer is formed over at least a portion of the doped region provided in step (a).
The above processing steps lead to the formation of ultra-shallow junctions in the Si-containing substrate since the transient enhanced diffusion of dopants like boron are substantially eliminated.